The demand exists for further improvement in the degree of integration of semiconductor integrated circuits. However, reducing the size of semiconductors has almost reached a limit. Therefore, technology for layering a plurality of chips, i.e. three-dimensional layering technology, is being developed.
Three-dimensional layering technology mainly uses a TSV (Through Silicon Via) as wiring and a terminal to connect chips, i.e. as a connection between chips. A TSV is formed by etching a through-hole in a silicon substrate and filling the hole with conductive material such as copper. Typically, the diameter of a TSV is between several μm and several dozen μm, whereas the depth of a TSV is several hundred μm. Forming a large number of TSVs on a chip raises the density of the TSVs, making TSVs with a high aspect ratio (height/diameter) necessary. As the aspect ratio increases, it becomes more difficult to fill the TSV, and the occurrence of cavities referred to as “voids” becomes more common. A void degrades the conducting state of a TSV, hampering inter-chip connection through the TSV. Furthermore, since TSVs are a fine structure, it is difficult to accurately align TSVs when layering two chips. Accordingly, in order to confirm a proper connection through a TSV between layered chips, three-dimensional layering technology also requires technology for testing both the conducting state of a TSV itself and the TSV-chip conducting state. Additionally, to maintain a high yield of integrated circuits manufactured using three-dimensional layering technology (hereinafter referred to as “three-dimensional integrated circuits”), it is necessary to test the circuits implemented on each chip before layering a plurality of chips. Therefore, in order to improve the yield upon manufacturing three-dimensional integrated circuits, it is effective to perform a test on each chip before layering a plurality of chips (Pre-Bonding Test). After layering a plurality of chips, a test is performed on the plurality of layered chips (Post-Bonding Test), and at this point it is effective to perform both a test on each chip as well as a test on the TSVs connecting chips. As compared to tests for a single layer integrated circuit, tests for three-dimensional integrated circuits are therefore complex. As a result, in order to reduce the cost of manufacturing three-dimensional integrated circuits, it is necessary to improve the efficiency of these two types of tests and to reduce the number of steps involved.
DFT (Design for Testability) is a known technology for improving the efficiency of tests performed when manufacturing integrated circuits. DFT is technology that aims to make a test for an integrated circuit easy by incorporating a circuit necessary to perform the test into the integrated circuit in the design phase. The technology disclosed in Non-Patent Literature 1 is an example of DFT that targets three-dimensional integrated circuits. This technology is an extension of the standard DFT in IEEE 1149.1/4/6 to three-dimensional integrated circuits. Specifically, a test circuit, such as a TAM (Test Access Mechanism), a scan chain, a TDC (Test Data Compression), or a BIST (Built-In Self-Test), for testing circuits implemented on a chip is incorporated into each chip. A dedicated testing pad is also provided in each chip for accessing to the test circuit from an external source. Each chip is also provided with a dedicated terminal for receiving a test signal from another chip which lies below the level of the chip, and with a switch for selectively connecting the test circuit either the dedicated terminal or the dedicated testing pad. When several tests are performed on each chip before a plurality of chips is layered, the switch in each chip connects the test circuit with the dedicated testing pad. As a result, the external test signal is sent through the dedicated testing pad to the test circuit of each chip. On the other hand, when tests are performed on the layered chips after a plurality of chips is layered, the switch connects the test circuit in each chip to the dedicated terminal. As a result, a test signal is sent from the bottom substrate through the dedicated terminal between chips to the test circuit of each chip.
The three-dimensional integrated circuit disclosed in Patent Literature 1 is also known. In this three-dimensional integrated circuit, each chip is provided with a mounting terminal and a testing terminal. Each terminal is a TSV. The mounting terminal is connected to a circuit implemented on the chip. The testing terminal is separated from a circuit implemented on the chip. Upon layering a plurality of chips, the testing terminals of the chips form a transmission path for a testing signal. When a new chip is further layered on top of this group of chips, the mounting terminal of the new chip is connected to the testing terminals of the group of chips, and a test signal is sent to the new chip through the testing terminals. In this way, the circuits implemented on the new chip and the mounting terminal can be tested. If the test results indicate no defects in the circuits and the mounting terminal, the mounting terminal of the new chip is reconnected to the mounting terminals of the group of chips. It is thus possible to layer only chips without any defects.
Patent Literature 2 discloses the following integrated circuit. Two chips in the integrated circuit are connected to each other through a plurality of connection terminals by wire bonding. A test output control circuit is implemented on one of the chips, and an expected value judgment circuit is implemented on the other chip. The test output control circuit outputs test data to the plurality of connection terminals. The test data is set so that the logical level is flipped between two adjacent connection terminals. The expected value judgment circuit receives the test data from the plurality of connection terminals and judges whether each piece of received test data matches the test data output by the test output control circuit. The judgment results indicate not only whether any of the connection terminals is disconnected, but also whether any pair of adjacent connection terminals has short-circuited.